In general, the problem of how to improve a processor's performance over standard techniques, for example, the problems of how to make a design that is more scalable, how to extend the design with new instructions, and how to simplify a processor's implementation are important processor development issues that need to be solved for future processor products. One important reason why instruction and program execution is held back from reaching higher performance levels is that in the sequential code execution model that is inherent in today's commercially available processors, fetched instructions are required to be executed at the earliest possible time in a manner which does not violate the logical program flow. This requirement tightly couples the fetching of instructions with their scheduled execution at the earliest possible time in a pipeline flow. In typical operation under this sequential code execution model, a fetched instruction, even if it is among a group of fetched instructions and even if the implementation supports out of order execution, is still scheduled for execution as quickly as possible. This coupling of an instruction fetched from program memory with its earliest possible execution in pipelines of varying depth and complexity is one of the key attributes of such current designs that affect their performance, scalability, extensibility, and difficulty of implementation.